Method and system for analyzing wire-only changes to a microprocessor design using delta model
A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a del...
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creator | SPENCER ALEXANDER KOOS WILLIAMSON BARRY DUANE |
description | A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model. |
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A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020611&DB=EPODOC&CC=US&NR=6405352B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020611&DB=EPODOC&CC=US&NR=6405352B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SPENCER ALEXANDER KOOS</creatorcontrib><creatorcontrib>WILLIAMSON BARRY DUANE</creatorcontrib><title>Method and system for analyzing wire-only changes to a microprocessor design using delta model</title><description>A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNy0EKwjAQheFuXIh6h7lAQa31ABXFjSt1axmSaRpIMyETkXh6I3gAVz8PvjevHhdKI2tAr0GyJJpg4Fgmuvy23sDLRqrZuwxqRG9IIDEgTFZFDpEViRSvSazx8JTvRZNLRXDpspoN6IRWvy4qOB1vh3NNgXuSgIo8pf5-3e_WbdNuu03zB_kA0wg8bA</recordid><startdate>20020611</startdate><enddate>20020611</enddate><creator>SPENCER ALEXANDER KOOS</creator><creator>WILLIAMSON BARRY DUANE</creator><scope>EVB</scope></search><sort><creationdate>20020611</creationdate><title>Method and system for analyzing wire-only changes to a microprocessor design using delta model</title><author>SPENCER ALEXANDER KOOS ; WILLIAMSON BARRY DUANE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6405352B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SPENCER ALEXANDER KOOS</creatorcontrib><creatorcontrib>WILLIAMSON BARRY DUANE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SPENCER ALEXANDER KOOS</au><au>WILLIAMSON BARRY DUANE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and system for analyzing wire-only changes to a microprocessor design using delta model</title><date>2002-06-11</date><risdate>2002</risdate><abstract>A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Method and system for analyzing wire-only changes to a microprocessor design using delta model |
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