Method for adhering and sealing a silicon chip in an integrated circuit package

Method for adhering and sealing a silicon chip in an integrated circuit package

A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100)...

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Hauptverfasser: YEW CHEE KIANG, ENG KIAN TENG, CHAN BOON PEW, TOH TUCK FOOK, CHAN MIN YU, LOW SIU WAF, GOH JING SUA, YEE PAK HONG
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator YEW CHEE KIANG
ENG KIAN TENG
CHAN BOON PEW
TOH TUCK FOOK
CHAN MIN YU
LOW SIU WAF
GOH JING SUA
YEE PAK HONG
description A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method for adhering and sealing a silicon chip in an integrated circuit package
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