System and method for concurrent placement of gates and associated wiring

A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.

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Hauptverfasser:	YEAP GARY K, TARAPOREVALA FEROZE PESHOTAN, SARRAFZADEH MAJID, PILEGGI LAWRENCE, GAO TONG, BOYLE DOUGLAS B
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	YEAP GARY K TARAPOREVALA FEROZE PESHOTAN SARRAFZADEH MAJID PILEGGI LAWRENCE GAO TONG BOYLE DOUGLAS B
description	A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.
format	Patent
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title	System and method for concurrent placement of gates and associated wiring
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