Cache blocking of specific data to secondary cache with a first and a second OR circuit

A cache blocking mechanism ensures that transient data is not stored in a secondary cache of a router by managing a designated set of buffers in a main memory of the router. The mechanism defines a window of virtual addresses that map to predetermined physical memory addresses associated with the se...

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Bibliographische Detailangaben

Hauptverfasser:	ROSEN JONATHAN, HILLA STEPHEN C
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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