Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer

An enhanced memory algorithmic processor ("MAP") architecture for multiprocessor computer systems comprises an assembly that may comprise, for example, field programmable gate arrays ("FPGAs") functioning as the memory algorithmic processors. The MAP elements may further include...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	LESKAR PAUL A, HUPPENTHAL JON M
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!