Reinforced integrated circuits
A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 mum. The thickness of the conductive structure is sufficiently great as to effectively protect any layer...
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creator | HEIDENREICH, III JOHN E VOLANT RICHARD P SAMBUCETTI CARLOS J RUBINO JUDITH M PETRARCA KEVIN S WALKER GEORGE F |
description | A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 mum. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer. |
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The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020115&DB=EPODOC&CC=US&NR=6339024B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020115&DB=EPODOC&CC=US&NR=6339024B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HEIDENREICH, III JOHN E</creatorcontrib><creatorcontrib>VOLANT RICHARD P</creatorcontrib><creatorcontrib>SAMBUCETTI CARLOS J</creatorcontrib><creatorcontrib>RUBINO JUDITH M</creatorcontrib><creatorcontrib>PETRARCA KEVIN S</creatorcontrib><creatorcontrib>WALKER GEORGE F</creatorcontrib><title>Reinforced integrated circuits</title><description>A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 mum. 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In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJALSs3MS8svSk5NUcjMK0lNL0osATKTM4uSSzNLinkYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSXxosJmxsaWBkYmToTERSgDYtCSZ</recordid><startdate>20020115</startdate><enddate>20020115</enddate><creator>HEIDENREICH, III JOHN E</creator><creator>VOLANT RICHARD P</creator><creator>SAMBUCETTI CARLOS J</creator><creator>RUBINO JUDITH M</creator><creator>PETRARCA KEVIN S</creator><creator>WALKER GEORGE F</creator><scope>EVB</scope></search><sort><creationdate>20020115</creationdate><title>Reinforced integrated circuits</title><author>HEIDENREICH, III JOHN E ; VOLANT RICHARD P ; SAMBUCETTI CARLOS J ; RUBINO JUDITH M ; PETRARCA KEVIN S ; WALKER GEORGE F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6339024B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HEIDENREICH, III JOHN E</creatorcontrib><creatorcontrib>VOLANT RICHARD P</creatorcontrib><creatorcontrib>SAMBUCETTI CARLOS J</creatorcontrib><creatorcontrib>RUBINO JUDITH M</creatorcontrib><creatorcontrib>PETRARCA KEVIN S</creatorcontrib><creatorcontrib>WALKER GEORGE F</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HEIDENREICH, III JOHN E</au><au>VOLANT RICHARD P</au><au>SAMBUCETTI CARLOS J</au><au>RUBINO JUDITH M</au><au>PETRARCA KEVIN S</au><au>WALKER GEORGE F</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Reinforced integrated circuits</title><date>2002-01-15</date><risdate>2002</risdate><abstract>A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 mum. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Reinforced integrated circuits |
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