Method of fabricating a non-volatile semiconductor device

A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alte...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BRACCHITTA JOHN A, NAKOS JAMES S
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator BRACCHITTA JOHN A
NAKOS JAMES S
description A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6339015B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6339015B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6339015B13</originalsourceid><addsrcrecordid>eNrjZLD0TS3JyE9RyE9TSEtMKspMTizJzEtXSFTIy8_TLcvPAXJzUhWKU3Mzk_PzUkqTS_KLFFJSyzKTU3kYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSXxosJmxsaWBoamToTERSgDnxy5-</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of fabricating a non-volatile semiconductor device</title><source>esp@cenet</source><creator>BRACCHITTA JOHN A ; NAKOS JAMES S</creator><creatorcontrib>BRACCHITTA JOHN A ; NAKOS JAMES S</creatorcontrib><description>A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020115&amp;DB=EPODOC&amp;CC=US&amp;NR=6339015B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020115&amp;DB=EPODOC&amp;CC=US&amp;NR=6339015B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BRACCHITTA JOHN A</creatorcontrib><creatorcontrib>NAKOS JAMES S</creatorcontrib><title>Method of fabricating a non-volatile semiconductor device</title><description>A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD0TS3JyE9RyE9TSEtMKspMTizJzEtXSFTIy8_TLcvPAXJzUhWKU3Mzk_PzUkqTS_KLFFJSyzKTU3kYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSXxosJmxsaWBoamToTERSgDnxy5-</recordid><startdate>20020115</startdate><enddate>20020115</enddate><creator>BRACCHITTA JOHN A</creator><creator>NAKOS JAMES S</creator><scope>EVB</scope></search><sort><creationdate>20020115</creationdate><title>Method of fabricating a non-volatile semiconductor device</title><author>BRACCHITTA JOHN A ; NAKOS JAMES S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6339015B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BRACCHITTA JOHN A</creatorcontrib><creatorcontrib>NAKOS JAMES S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BRACCHITTA JOHN A</au><au>NAKOS JAMES S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of fabricating a non-volatile semiconductor device</title><date>2002-01-15</date><risdate>2002</risdate><abstract>A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US6339015B1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method of fabricating a non-volatile semiconductor device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T15%3A50%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BRACCHITTA%20JOHN%20A&rft.date=2002-01-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6339015B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true