Clock input buffer with noise suppression

A circuit is designed with a delay circuit (300) coupled to receive a clock input signal (CLK) and a control signal (DFT). The control signal has a first logic state and a second logic state. The delay circuit produces a clock control signal (*CLK) at a first time in response to the first logic stat...

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Bibliographische Detailangaben

Hauptverfasser:	BROWN JASON M, PENNEY DANIEL B, WALDROP WILLIAM C
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES
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