Scannable circuits, systems, and methods implementing transistors having differing threshold voltages

An integrated circuit device (10) comprising a conductor (11) for receiving a scan data signal. The integrated circuit device further comprises a plurality of storage circuit devices (SC1 through SC4), and each of those storage circuits has a data input and a data output. A first (SC1) of the plurality of storage circuit devices is coupled to receive the scan data signal at its data input. Moreover, each of the plurality of storage circuit devices other than the first of the plurality of storage circuit devices is coupled to receive at its data input a scan data bit as output from another one of the plurality of storage circuit devices as part of the scan data signal, thereby forming a clocked scan path through the integrated circuit device. The integrated circuit device further comprises a scannable multiplexer circuit (14) having an output (24) coupled to a data input of one (e.g., SC1) of the plurality of storage circuits. The scannable multiplexer circuit comprises a first input (DS1) for receiving a scan data bit from the scan data signal and a second input (DN1) for receiving a normal operations data bit. The scannable multiplexer circuit further comprises a first transistor device (22N) having its source/drain conductive path coupled between the first input and the output of the scannable multiplexer circuit, and having a first threshold voltage, and also a second transistor device (20N) having its source/drain conductive path coupled between the second input and the output of the scannable multiplexer circuit, and having a second threshold voltage. The first threshold voltage is larger in absolute value than the second threshold voltage.