Power transistor with silicided gate and contacts
A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also ha...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | SMITH JEFFREY P ERDELJAC JOHN P EFLAND TAYLOR R YANG JAU-YUANN ARCH JOHN K HUTTER LOUIS N THOMPSON C. MATTHEW YUAN HAN-TZONG MURPHY MARY ANN |
| description | A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78). |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6284669B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6284669B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6284669B13</originalsourceid><addsrcrecordid>eNrjZDAMyC9PLVIoKUrMK84sLskvUijPLMlQKM7MyUzOTElNUUhPLElVSMxLUUjOzytJTC4p5mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZkYWJmZmlk6GxkQoAQBhJSu5</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Power transistor with silicided gate and contacts</title><source>esp@cenet</source><creator>SMITH JEFFREY P ; ERDELJAC JOHN P ; EFLAND TAYLOR R ; YANG JAU-YUANN ; ARCH JOHN K ; HUTTER LOUIS N ; THOMPSON C. MATTHEW ; YUAN HAN-TZONG ; MURPHY MARY ANN</creator><creatorcontrib>SMITH JEFFREY P ; ERDELJAC JOHN P ; EFLAND TAYLOR R ; YANG JAU-YUANN ; ARCH JOHN K ; HUTTER LOUIS N ; THOMPSON C. MATTHEW ; YUAN HAN-TZONG ; MURPHY MARY ANN</creatorcontrib><description>A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010904&DB=EPODOC&CC=US&NR=6284669B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010904&DB=EPODOC&CC=US&NR=6284669B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SMITH JEFFREY P</creatorcontrib><creatorcontrib>ERDELJAC JOHN P</creatorcontrib><creatorcontrib>EFLAND TAYLOR R</creatorcontrib><creatorcontrib>YANG JAU-YUANN</creatorcontrib><creatorcontrib>ARCH JOHN K</creatorcontrib><creatorcontrib>HUTTER LOUIS N</creatorcontrib><creatorcontrib>THOMPSON C. MATTHEW</creatorcontrib><creatorcontrib>YUAN HAN-TZONG</creatorcontrib><creatorcontrib>MURPHY MARY ANN</creatorcontrib><title>Power transistor with silicided gate and contacts</title><description>A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAMyC9PLVIoKUrMK84sLskvUijPLMlQKM7MyUzOTElNUUhPLElVSMxLUUjOzytJTC4p5mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZkYWJmZmlk6GxkQoAQBhJSu5</recordid><startdate>20010904</startdate><enddate>20010904</enddate><creator>SMITH JEFFREY P</creator><creator>ERDELJAC JOHN P</creator><creator>EFLAND TAYLOR R</creator><creator>YANG JAU-YUANN</creator><creator>ARCH JOHN K</creator><creator>HUTTER LOUIS N</creator><creator>THOMPSON C. MATTHEW</creator><creator>YUAN HAN-TZONG</creator><creator>MURPHY MARY ANN</creator><scope>EVB</scope></search><sort><creationdate>20010904</creationdate><title>Power transistor with silicided gate and contacts</title><author>SMITH JEFFREY P ; ERDELJAC JOHN P ; EFLAND TAYLOR R ; YANG JAU-YUANN ; ARCH JOHN K ; HUTTER LOUIS N ; THOMPSON C. MATTHEW ; YUAN HAN-TZONG ; MURPHY MARY ANN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6284669B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SMITH JEFFREY P</creatorcontrib><creatorcontrib>ERDELJAC JOHN P</creatorcontrib><creatorcontrib>EFLAND TAYLOR R</creatorcontrib><creatorcontrib>YANG JAU-YUANN</creatorcontrib><creatorcontrib>ARCH JOHN K</creatorcontrib><creatorcontrib>HUTTER LOUIS N</creatorcontrib><creatorcontrib>THOMPSON C. MATTHEW</creatorcontrib><creatorcontrib>YUAN HAN-TZONG</creatorcontrib><creatorcontrib>MURPHY MARY ANN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SMITH JEFFREY P</au><au>ERDELJAC JOHN P</au><au>EFLAND TAYLOR R</au><au>YANG JAU-YUANN</au><au>ARCH JOHN K</au><au>HUTTER LOUIS N</au><au>THOMPSON C. MATTHEW</au><au>YUAN HAN-TZONG</au><au>MURPHY MARY ANN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Power transistor with silicided gate and contacts</title><date>2001-09-04</date><risdate>2001</risdate><abstract>A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US6284669B1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Power transistor with silicided gate and contacts |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T14%3A44%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SMITH%20JEFFREY%20P&rft.date=2001-09-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6284669B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |