Method of on-chip interconnect design

A method of on-chip interconnect design in an integrated circuit (IC) is provided. Fast circuit simulations of each net constituting the IC are performed for noise margin and slew rate analysis. A resistor/capacitor (RC) network for each net is generated from net lengths, and assignments of parasiti...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BOWEN MICHAEL ALEXANDER, SMITH HOWARD HAROLD, CASES MOISES
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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