Timing recovery loop circuit in a receiver of a modem

A method and apparatus for timing recovery in modem receivers. The timing recovery circuit includes a voltage controlled oscillator for controlling the voltage controlled sampling frequency of an analog-to-digital converter. The oscillator generates a timing clock that is dependent on an average phase error signal calculated from Nyquist signals of the input signal. A phase detector circuit is used for generating an instantaneous phase error signal of the in-phase and quadrature-phase signals. A digital loop filter receives the instantaneous phase error signal over time to generate the average phase error signal. The average phase error signal is conditioned further (after conversion to analog) by an analog loop filter such that the average phase error signal adjusts the timing clock generated by the oscillator. The low pass filter provides control of the acquisition and steady state operations by changing the gain and pole parameters of the filter. This control enables fast timing acquisition and low noise with reduced phase jitter during steady state operation.