Method and apparatus for forming plugs in vias of a circuit board layer
A method of forming one or more plugs in a circuit board layer is described which includes providing the circuit board layer, the circuit board layer having a first surface, a second surface, and defining a via containing a plug material in a volatile solvent, evaporating the volatile solvent, and c...
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creator | BIUNNO NICHOLAS BRYAN SCOTT K |
description | A method of forming one or more plugs in a circuit board layer is described which includes providing the circuit board layer, the circuit board layer having a first surface, a second surface, and defining a via containing a plug material in a volatile solvent, evaporating the volatile solvent, and curing the plug material. A product made according to the above method is also described. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6276055B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6276055B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6276055B13</originalsourceid><addsrcrecordid>eNrjZHD3TS3JyE9RSMwD4oKCxKLEktJihbT8IhDOzcxLVyjIKU0vVsjMUyjLTCxWyE9TSFRIzixKLs0sUUjKTyxKUchJrEwt4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZkbmZgampk6GxkQoAQDDHDMd</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for forming plugs in vias of a circuit board layer</title><source>esp@cenet</source><creator>BIUNNO NICHOLAS ; BRYAN SCOTT K</creator><creatorcontrib>BIUNNO NICHOLAS ; BRYAN SCOTT K</creatorcontrib><description>A method of forming one or more plugs in a circuit board layer is described which includes providing the circuit board layer, the circuit board layer having a first surface, a second surface, and defining a via containing a plug material in a volatile solvent, evaporating the volatile solvent, and curing the plug material. A product made according to the above method is also described.</description><edition>7</edition><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010821&DB=EPODOC&CC=US&NR=6276055B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010821&DB=EPODOC&CC=US&NR=6276055B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BIUNNO NICHOLAS</creatorcontrib><creatorcontrib>BRYAN SCOTT K</creatorcontrib><title>Method and apparatus for forming plugs in vias of a circuit board layer</title><description>A method of forming one or more plugs in a circuit board layer is described which includes providing the circuit board layer, the circuit board layer having a first surface, a second surface, and defining a via containing a plug material in a volatile solvent, evaporating the volatile solvent, and curing the plug material. A product made according to the above method is also described.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD3TS3JyE9RSMwD4oKCxKLEktJihbT8IhDOzcxLVyjIKU0vVsjMUyjLTCxWyE9TSFRIzixKLs0sUUjKTyxKUchJrEwt4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZkbmZgampk6GxkQoAQDDHDMd</recordid><startdate>20010821</startdate><enddate>20010821</enddate><creator>BIUNNO NICHOLAS</creator><creator>BRYAN SCOTT K</creator><scope>EVB</scope></search><sort><creationdate>20010821</creationdate><title>Method and apparatus for forming plugs in vias of a circuit board layer</title><author>BIUNNO NICHOLAS ; BRYAN SCOTT K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6276055B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><toplevel>online_resources</toplevel><creatorcontrib>BIUNNO NICHOLAS</creatorcontrib><creatorcontrib>BRYAN SCOTT K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BIUNNO NICHOLAS</au><au>BRYAN SCOTT K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for forming plugs in vias of a circuit board layer</title><date>2001-08-21</date><risdate>2001</risdate><abstract>A method of forming one or more plugs in a circuit board layer is described which includes providing the circuit board layer, the circuit board layer having a first surface, a second surface, and defining a via containing a plug material in a volatile solvent, evaporating the volatile solvent, and curing the plug material. A product made according to the above method is also described.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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language | eng |
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subjects | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS |
title | Method and apparatus for forming plugs in vias of a circuit board layer |
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