Processor powerdown operation using intermittent bursts of instruction clock

An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed em...

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Hauptverfasser: BAYS LAURENCE E, NIESCIER RICHARD JOSEPH, FADAVI-ARDEKANI JALIL, FITCH KENNETH DANIEL
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creator BAYS LAURENCE E
NIESCIER RICHARD JOSEPH
FADAVI-ARDEKANI JALIL
FITCH KENNETH DANIEL
description An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6275948B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6275948B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6275948B13</originalsourceid><addsrcrecordid>eNqNyj0KAkEMQOFpLES9Qy5g4b-2imJhIaj1MmazMrgmQ5Jhr6-IB7B68Pj64XRWQTIThSwdaS0dg2TS6EkYiiV-QGInfSV3Yod7UXMDaT7bXAt-IbaCz2HoNbE1Gv06CHDYX3fHMWWpyHJEYvLqdllOV4vNfL2dzP4gb_RhNx4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Processor powerdown operation using intermittent bursts of instruction clock</title><source>esp@cenet</source><creator>BAYS LAURENCE E ; NIESCIER RICHARD JOSEPH ; FADAVI-ARDEKANI JALIL ; FITCH KENNETH DANIEL</creator><creatorcontrib>BAYS LAURENCE E ; NIESCIER RICHARD JOSEPH ; FADAVI-ARDEKANI JALIL ; FITCH KENNETH DANIEL</creatorcontrib><description>An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20010814&amp;DB=EPODOC&amp;CC=US&amp;NR=6275948B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20010814&amp;DB=EPODOC&amp;CC=US&amp;NR=6275948B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BAYS LAURENCE E</creatorcontrib><creatorcontrib>NIESCIER RICHARD JOSEPH</creatorcontrib><creatorcontrib>FADAVI-ARDEKANI JALIL</creatorcontrib><creatorcontrib>FITCH KENNETH DANIEL</creatorcontrib><title>Processor powerdown operation using intermittent bursts of instruction clock</title><description>An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyj0KAkEMQOFpLES9Qy5g4b-2imJhIaj1MmazMrgmQ5Jhr6-IB7B68Pj64XRWQTIThSwdaS0dg2TS6EkYiiV-QGInfSV3Yod7UXMDaT7bXAt-IbaCz2HoNbE1Gv06CHDYX3fHMWWpyHJEYvLqdllOV4vNfL2dzP4gb_RhNx4</recordid><startdate>20010814</startdate><enddate>20010814</enddate><creator>BAYS LAURENCE E</creator><creator>NIESCIER RICHARD JOSEPH</creator><creator>FADAVI-ARDEKANI JALIL</creator><creator>FITCH KENNETH DANIEL</creator><scope>EVB</scope></search><sort><creationdate>20010814</creationdate><title>Processor powerdown operation using intermittent bursts of instruction clock</title><author>BAYS LAURENCE E ; NIESCIER RICHARD JOSEPH ; FADAVI-ARDEKANI JALIL ; FITCH KENNETH DANIEL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6275948B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>BAYS LAURENCE E</creatorcontrib><creatorcontrib>NIESCIER RICHARD JOSEPH</creatorcontrib><creatorcontrib>FADAVI-ARDEKANI JALIL</creatorcontrib><creatorcontrib>FITCH KENNETH DANIEL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BAYS LAURENCE E</au><au>NIESCIER RICHARD JOSEPH</au><au>FADAVI-ARDEKANI JALIL</au><au>FITCH KENNETH DANIEL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Processor powerdown operation using intermittent bursts of instruction clock</title><date>2001-08-14</date><risdate>2001</risdate><abstract>An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Processor powerdown operation using intermittent bursts of instruction clock
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