Bitline latch switching circuit for floating gate memory device requiring zero volt programming voltage

A floating gate memory device that includes a column latch circuit that is isolated from a series of bitlines by PMOS pass transistors controlled by a bitline latch switch circuit. The bitline latch switch circuit selectively applies either +5 V or -2 V signals to the gate terminals of the PMOS pass...

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Bibliographische Detailangaben

Hauptverfasser:	SHOKOUHI FARSHID, AHRENS MICHAEL G
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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