Combined chemical mechanical polishing and reactive ion etching process

A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemica...

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Hauptverfasser:	MACDONALD MICHAEL J, MLYNKO WALTER E, MURRAY MARK P, PETERSON KIRK D, LANDERS WILLIAM F, FERENCE THOMAS G
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	MACDONALD MICHAEL J MLYNKO WALTER E MURRAY MARK P PETERSON KIRK D LANDERS WILLIAM F FERENCE THOMAS G
description	A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6221775B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6221775B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6221775B13</originalsourceid><addsrcrecordid>eNqNijsOwjAQBd1QIOAOewGKBEF6Ij49UEfL5oFXstdWbHF-pIgDUM1IM0t36VN8qmEk8YgqHChCPNusOQUtXu1NbCNNYKn6AWkyQpU55CkJSlm7xYtDwebHlaPz6d5ft8hpQMksMNThcTu0bdN1-2Oz-2P5AhCwM9A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Combined chemical mechanical polishing and reactive ion etching process</title><source>esp@cenet</source><creator>MACDONALD MICHAEL J ; MLYNKO WALTER E ; MURRAY MARK P ; PETERSON KIRK D ; LANDERS WILLIAM F ; FERENCE THOMAS G</creator><creatorcontrib>MACDONALD MICHAEL J ; MLYNKO WALTER E ; MURRAY MARK P ; PETERSON KIRK D ; LANDERS WILLIAM F ; FERENCE THOMAS G</creatorcontrib><description>A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010424&DB=EPODOC&CC=US&NR=6221775B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010424&DB=EPODOC&CC=US&NR=6221775B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MACDONALD MICHAEL J</creatorcontrib><creatorcontrib>MLYNKO WALTER E</creatorcontrib><creatorcontrib>MURRAY MARK P</creatorcontrib><creatorcontrib>PETERSON KIRK D</creatorcontrib><creatorcontrib>LANDERS WILLIAM F</creatorcontrib><creatorcontrib>FERENCE THOMAS G</creatorcontrib><title>Combined chemical mechanical polishing and reactive ion etching process</title><description>A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNijsOwjAQBd1QIOAOewGKBEF6Ij49UEfL5oFXstdWbHF-pIgDUM1IM0t36VN8qmEk8YgqHChCPNusOQUtXu1NbCNNYKn6AWkyQpU55CkJSlm7xYtDwebHlaPz6d5ft8hpQMksMNThcTu0bdN1-2Oz-2P5AhCwM9A</recordid><startdate>20010424</startdate><enddate>20010424</enddate><creator>MACDONALD MICHAEL J</creator><creator>MLYNKO WALTER E</creator><creator>MURRAY MARK P</creator><creator>PETERSON KIRK D</creator><creator>LANDERS WILLIAM F</creator><creator>FERENCE THOMAS G</creator><scope>EVB</scope></search><sort><creationdate>20010424</creationdate><title>Combined chemical mechanical polishing and reactive ion etching process</title><author>MACDONALD MICHAEL J ; MLYNKO WALTER E ; MURRAY MARK P ; PETERSON KIRK D ; LANDERS WILLIAM F ; FERENCE THOMAS G</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6221775B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MACDONALD MICHAEL J</creatorcontrib><creatorcontrib>MLYNKO WALTER E</creatorcontrib><creatorcontrib>MURRAY MARK P</creatorcontrib><creatorcontrib>PETERSON KIRK D</creatorcontrib><creatorcontrib>LANDERS WILLIAM F</creatorcontrib><creatorcontrib>FERENCE THOMAS G</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MACDONALD MICHAEL J</au><au>MLYNKO WALTER E</au><au>MURRAY MARK P</au><au>PETERSON KIRK D</au><au>LANDERS WILLIAM F</au><au>FERENCE THOMAS G</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Combined chemical mechanical polishing and reactive ion etching process</title><date>2001-04-24</date><risdate>2001</risdate><abstract>A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Combined chemical mechanical polishing and reactive ion etching process
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