Chip scale package and manufacturing method thereof

A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball. The chip scale package is electrically connected to outside through the solder balls. The slot of the substrate and the periphery of the semiconductor chip are sealed by an integrally formed package body. The present invention is characterized in that the encapsulation process of the chip scale package is carried out by a single step of dispensing and curing, so as to increase UPH (unit per hour) thereby shortening encapsulation cycle time. Moreover, the occurrence of flash on the substrate surface around the slot during encapsulation can be reduced, thereby assuring the solder joint reliability of the solder pads.