Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline

An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A subset of the t...

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Bibliographische Detailangaben

Hauptverfasser:	HICKS, JAMES E, WEIHL, WILLIAM E, DEAN, JEFFREY, MCLELLAN, EDWARD J, WALDSPURGER, CARL A, CHRYSOS, GEORGE Z, LEIBHOLZ, DANIEL L
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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