Method for manufacturing a thin oxide for use in semiconductor integrated circuits
A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containin...
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creator | LII YEONG-JYH TOM CRABTREE PHILLIP EARL TSENG HSING-HUANG WU WEI EDWIN |
description | A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6146948A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6146948A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6146948A3</originalsourceid><addsrcrecordid>eNqFirsKwkAQAK-xEPUb3B-wEEPQMohiY-OjDsveXrJg9sLdHvj5BrG3GpiZubtd2froIcQEA2oJSFaSaAcI1otCfIvnby6ZYRKZB6GovpBNUtS4S2jsgSRREctLNwv4yrz6ceHW59PjeNnwGFvOIxIrW_u819uqPlT7Zvf_-ABZizfP</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for manufacturing a thin oxide for use in semiconductor integrated circuits</title><source>esp@cenet</source><creator>LII; YEONG-JYH TOM ; CRABTREE; PHILLIP EARL ; TSENG; HSING-HUANG ; WU; WEI EDWIN</creator><creatorcontrib>LII; YEONG-JYH TOM ; CRABTREE; PHILLIP EARL ; TSENG; HSING-HUANG ; WU; WEI EDWIN</creatorcontrib><description>A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001114&DB=EPODOC&CC=US&NR=6146948A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001114&DB=EPODOC&CC=US&NR=6146948A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LII; YEONG-JYH TOM</creatorcontrib><creatorcontrib>CRABTREE; PHILLIP EARL</creatorcontrib><creatorcontrib>TSENG; HSING-HUANG</creatorcontrib><creatorcontrib>WU; WEI EDWIN</creatorcontrib><title>Method for manufacturing a thin oxide for use in semiconductor integrated circuits</title><description>A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFirsKwkAQAK-xEPUb3B-wEEPQMohiY-OjDsveXrJg9sLdHvj5BrG3GpiZubtd2froIcQEA2oJSFaSaAcI1otCfIvnby6ZYRKZB6GovpBNUtS4S2jsgSRREctLNwv4yrz6ceHW59PjeNnwGFvOIxIrW_u819uqPlT7Zvf_-ABZizfP</recordid><startdate>20001114</startdate><enddate>20001114</enddate><creator>LII; YEONG-JYH TOM</creator><creator>CRABTREE; PHILLIP EARL</creator><creator>TSENG; HSING-HUANG</creator><creator>WU; WEI EDWIN</creator><scope>EVB</scope></search><sort><creationdate>20001114</creationdate><title>Method for manufacturing a thin oxide for use in semiconductor integrated circuits</title><author>LII; YEONG-JYH TOM ; CRABTREE; PHILLIP EARL ; TSENG; HSING-HUANG ; WU; WEI EDWIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6146948A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LII; YEONG-JYH TOM</creatorcontrib><creatorcontrib>CRABTREE; PHILLIP EARL</creatorcontrib><creatorcontrib>TSENG; HSING-HUANG</creatorcontrib><creatorcontrib>WU; WEI EDWIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LII; YEONG-JYH TOM</au><au>CRABTREE; PHILLIP EARL</au><au>TSENG; HSING-HUANG</au><au>WU; WEI EDWIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for manufacturing a thin oxide for use in semiconductor integrated circuits</title><date>2000-11-14</date><risdate>2000</risdate><abstract>A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Method for manufacturing a thin oxide for use in semiconductor integrated circuits |
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