Selectable self-timed replacement for self-resetting circuitry

A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the assertion of the data and the assertion of the valid signal. Circuitry is provided to enable the effective de-...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KLIM, PETER J, DURHAM, CHRISTOPHER MCCALL
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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