Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application

A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in a silicon substrate 10. A gate oxide layer is formed on device areas. A doped blanket polysilicon layer...

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Bibliographische Detailangaben

Hauptverfasser:	LIM, ENG HWA, PEY, KIN LEONG, SIAH, SOH YUN, CHAN, LAP, CHONG WEE
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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