Method and apparatus for performing lane arithmetic to perform network processing
A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for...
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creator | HARRIMAN EDWARD S LADWIG GEOFF |
description | A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for performing one's complement additions are included to quickly calculate Internet checksums. Furthermore, the SIMD processor includes several instructions for performing lane arithmetic. |
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A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for performing one's complement additions are included to quickly calculate Internet checksums. Furthermore, the SIMD processor includes several instructions for performing lane arithmetic.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000404&DB=EPODOC&CC=US&NR=6047304A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000404&DB=EPODOC&CC=US&NR=6047304A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HARRIMAN; EDWARD S</creatorcontrib><creatorcontrib>LADWIG; GEOFF</creatorcontrib><title>Method and apparatus for performing lane arithmetic to perform network processing</title><description>A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for performing one's complement additions are included to quickly calculate Internet checksums. Furthermore, the SIMD processor includes several instructions for performing lane arithmetic.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAj0TS3JyE9RSMwD4oKCxKLEktJihbT8IoWC1CIglZuZl66Qk5iXqpBYlFmSkZtakpmsUJIPk1XISy0pzy_KVigoyk9OLS4GquZhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqUBN8aHBZgYm5sYGJo7GhFUAAEBxN6Y</recordid><startdate>20000404</startdate><enddate>20000404</enddate><creator>HARRIMAN; EDWARD S</creator><creator>LADWIG; GEOFF</creator><scope>EVB</scope></search><sort><creationdate>20000404</creationdate><title>Method and apparatus for performing lane arithmetic to perform network processing</title><author>HARRIMAN; EDWARD S ; LADWIG; GEOFF</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6047304A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>HARRIMAN; EDWARD S</creatorcontrib><creatorcontrib>LADWIG; GEOFF</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HARRIMAN; EDWARD S</au><au>LADWIG; GEOFF</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for performing lane arithmetic to perform network processing</title><date>2000-04-04</date><risdate>2000</risdate><abstract>A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for performing one's complement additions are included to quickly calculate Internet checksums. Furthermore, the SIMD processor includes several instructions for performing lane arithmetic.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Method and apparatus for performing lane arithmetic to perform network processing |
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