Image display system
An image display system includes a display circuit which displays an image composed of a plurality of sub-images, an input circuit which inputs a certain image signal including at least one sub-image embedded in the certain image signal which is provided by at least one of fields and frames, a desig...
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creator | TSURUGA SADAO KITOU KOUJI SOMEYA RYUUICHI INOUE FUMIO KAWASAKI JIRO IMAI YASUHIRO NAGABAYASHI TAMOTSU SANO TSUYOSHI MASUDA KOUZOU ARAI IKUYA HIROSE MASATOSHI |
description | An image display system includes a display circuit which displays an image composed of a plurality of sub-images, an input circuit which inputs a certain image signal including at least one sub-image embedded in the certain image signal which is provided by at least one of fields and frames, a designating circuit which designates timings of composition positions of the sub-image on scan lines of the certain image, and one control circuit which controls at least one of an amplitude level and a DC level of image signals corresponding to an area of the sub-image detected by the timing designated by the designating circuit. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5978041A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5978041A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5978041A3</originalsourceid><addsrcrecordid>eNrjZBDxzE1MT1VIySwuyEmsVCiuLC5JzeVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfGhwaaW5hYGJoaOxoRVAADSliAn</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Image display system</title><source>esp@cenet</source><creator>TSURUGA; SADAO ; KITOU; KOUJI ; SOMEYA; RYUUICHI ; INOUE; FUMIO ; KAWASAKI; JIRO ; IMAI; YASUHIRO ; NAGABAYASHI; TAMOTSU ; SANO; TSUYOSHI ; MASUDA; KOUZOU ; ARAI; IKUYA ; HIROSE; MASATOSHI</creator><creatorcontrib>TSURUGA; SADAO ; KITOU; KOUJI ; SOMEYA; RYUUICHI ; INOUE; FUMIO ; KAWASAKI; JIRO ; IMAI; YASUHIRO ; NAGABAYASHI; TAMOTSU ; SANO; TSUYOSHI ; MASUDA; KOUZOU ; ARAI; IKUYA ; HIROSE; MASATOSHI</creatorcontrib><description>An image display system includes a display circuit which displays an image composed of a plurality of sub-images, an input circuit which inputs a certain image signal including at least one sub-image embedded in the certain image signal which is provided by at least one of fields and frames, a designating circuit which designates timings of composition positions of the sub-image on scan lines of the certain image, and one control circuit which controls at least one of an amplitude level and a DC level of image signals corresponding to an area of the sub-image detected by the timing designated by the designating circuit.</description><edition>6</edition><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19991102&DB=EPODOC&CC=US&NR=5978041A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19991102&DB=EPODOC&CC=US&NR=5978041A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TSURUGA; SADAO</creatorcontrib><creatorcontrib>KITOU; KOUJI</creatorcontrib><creatorcontrib>SOMEYA; RYUUICHI</creatorcontrib><creatorcontrib>INOUE; FUMIO</creatorcontrib><creatorcontrib>KAWASAKI; JIRO</creatorcontrib><creatorcontrib>IMAI; YASUHIRO</creatorcontrib><creatorcontrib>NAGABAYASHI; TAMOTSU</creatorcontrib><creatorcontrib>SANO; TSUYOSHI</creatorcontrib><creatorcontrib>MASUDA; KOUZOU</creatorcontrib><creatorcontrib>ARAI; IKUYA</creatorcontrib><creatorcontrib>HIROSE; MASATOSHI</creatorcontrib><title>Image display system</title><description>An image display system includes a display circuit which displays an image composed of a plurality of sub-images, an input circuit which inputs a certain image signal including at least one sub-image embedded in the certain image signal which is provided by at least one of fields and frames, a designating circuit which designates timings of composition positions of the sub-image on scan lines of the certain image, and one control circuit which controls at least one of an amplitude level and a DC level of image signals corresponding to an area of the sub-image detected by the timing designated by the designating circuit.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBDxzE1MT1VIySwuyEmsVCiuLC5JzeVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfGhwaaW5hYGJoaOxoRVAADSliAn</recordid><startdate>19991102</startdate><enddate>19991102</enddate><creator>TSURUGA; SADAO</creator><creator>KITOU; KOUJI</creator><creator>SOMEYA; RYUUICHI</creator><creator>INOUE; FUMIO</creator><creator>KAWASAKI; JIRO</creator><creator>IMAI; YASUHIRO</creator><creator>NAGABAYASHI; TAMOTSU</creator><creator>SANO; TSUYOSHI</creator><creator>MASUDA; KOUZOU</creator><creator>ARAI; IKUYA</creator><creator>HIROSE; MASATOSHI</creator><scope>EVB</scope></search><sort><creationdate>19991102</creationdate><title>Image display system</title><author>TSURUGA; SADAO ; KITOU; KOUJI ; SOMEYA; RYUUICHI ; INOUE; FUMIO ; KAWASAKI; JIRO ; IMAI; YASUHIRO ; NAGABAYASHI; TAMOTSU ; SANO; TSUYOSHI ; MASUDA; KOUZOU ; ARAI; IKUYA ; HIROSE; MASATOSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5978041A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><toplevel>online_resources</toplevel><creatorcontrib>TSURUGA; SADAO</creatorcontrib><creatorcontrib>KITOU; KOUJI</creatorcontrib><creatorcontrib>SOMEYA; RYUUICHI</creatorcontrib><creatorcontrib>INOUE; FUMIO</creatorcontrib><creatorcontrib>KAWASAKI; JIRO</creatorcontrib><creatorcontrib>IMAI; YASUHIRO</creatorcontrib><creatorcontrib>NAGABAYASHI; TAMOTSU</creatorcontrib><creatorcontrib>SANO; TSUYOSHI</creatorcontrib><creatorcontrib>MASUDA; KOUZOU</creatorcontrib><creatorcontrib>ARAI; IKUYA</creatorcontrib><creatorcontrib>HIROSE; MASATOSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TSURUGA; SADAO</au><au>KITOU; KOUJI</au><au>SOMEYA; RYUUICHI</au><au>INOUE; FUMIO</au><au>KAWASAKI; JIRO</au><au>IMAI; YASUHIRO</au><au>NAGABAYASHI; TAMOTSU</au><au>SANO; TSUYOSHI</au><au>MASUDA; KOUZOU</au><au>ARAI; IKUYA</au><au>HIROSE; MASATOSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Image display system</title><date>1999-11-02</date><risdate>1999</risdate><abstract>An image display system includes a display circuit which displays an image composed of a plurality of sub-images, an input circuit which inputs a certain image signal including at least one sub-image embedded in the certain image signal which is provided by at least one of fields and frames, a designating circuit which designates timings of composition positions of the sub-image on scan lines of the certain image, and one control circuit which controls at least one of an amplitude level and a DC level of image signals corresponding to an area of the sub-image detected by the timing designated by the designating circuit.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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language | eng |
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subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PICTORIAL COMMUNICATION, e.g. TELEVISION |
title | Image display system |
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