Semiconductor memory device having two P-well layout structure

Semiconductor memory device having two P-well layout structure

This invention relates to P- and N-well regions where inverters constituting an SRAM cell are formed. The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). With this layout, di...

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Hauptverfasser: HARA, HIROYUKI, MATSUI, MASATAKA
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator HARA
HIROYUKI
MATSUI
MASATAKA
description This invention relates to P- and N-well regions where inverters constituting an SRAM cell are formed. The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). With this layout, diffusion layers (ND1, ND2) within the P-well regions can be formed into simple shapes free from any bent portion, reducing the cell area.
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The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). 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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor memory device having two P-well layout structure
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