Memory control unit using preloaded values to generate optimal timing of memory control sequences between different memory segments

A memory controller is described that comprises individual control segments for controlling memory that is divided into individual pairs of memory segments. The programmable memory controller provides improved average access times for memory devices by reducing the number of wait cycles between memory operations. A common data bus is shared between the memory segments. However, each control segment provides individual sets of address and control lines to each memory segment so that control sequences can occur simultaneously between multiple control and memory segments. Accordingly, when a control sequence is in process within one segment, another control sequence can occur simultaneously in another segment. By overlapping control sequences in this fashion, the bandwidth of the data bus is increased by remaining idle less frequently. Each control segment comprises a plurality of synchronous countdown register timers. Each countdown register is loaded with a programmable value at the beginning of a control sequence within its control segment. The programmable value is subsequently decremented by a value of one ('counts down') upon each pulse of a system clock. Each counter counts down to a value of zero and then holds that value until another memory sequence begins in the control segment. A value of zero within a counter indicates to the other control segment(s) that a particular control sequence therein can begin.