Dual tunable direct digital synthesizer with a frequency programmable clock and method of tuning

A dual-tunable direct digital synthesizer is provided with a programmable frequency multiplier that multiplies a relatively low frequency fixed clock signal Fclk so that the output frequency Fo of the waveform is: Fo=(Fn/2N)x(MxFclk) where N is the resolution of the digital control word, the tuning word Fn is the value of the N-bit control word, M is the multiplication factor and M*Fclk is the DDS clock frequency. The multiplication factor and, hence, the DDS clock can be reduced to track changes in the output frequency thereby lowering the average power consumption. Because the synthesizer can generate the same output frequency using different tuning word-to-DDS clock ratios, it can be tuned for optimum SFDR over a narrow band around the desired output frequency. In other words, an "enhanced dynamic range band" in the harmonic and spurious performance can be mapped out for each frequency in the bandwidth.