Data processor with flexible data encryption

A data processor (20) which flexibly encrypts data within different address ranges includes an encryption determination circuit (50) to monitor an address conducted on an internal address bus (22) and when the address is within certain predefined ranges, perform encryption or decryption of address a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BROWN, DAVID L, POLANSKY, PAUL J, POMBO, RAUL A
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator BROWN
DAVID L
POLANSKY
PAUL J
POMBO
RAUL A
description A data processor (20) which flexibly encrypts data within different address ranges includes an encryption determination circuit (50) to monitor an address conducted on an internal address bus (22) and when the address is within certain predefined ranges, perform encryption or decryption of address and/or data. For example the encryption determination circuit (50) may be used to selectively enable a data encryption-decryption circuit (60). When the data encryption-decryption circuit (60) is disabled, data conducted on an internal data bus (23) becomes "cleartext", i.e., non-encrypted. In one embodiment, the data encryption-decryption is performed in partial dependence on the address itself, and the address conducted to the external address bus is itself selectively encrypted as well.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5892826A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5892826A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5892826A3</originalsourceid><addsrcrecordid>eNrjZNBxSSxJVCgoyk9OLS7OL1IozyzJUEjLSa3ITMpJVUgBSabmJRdVFpRk5ufxMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JL40GBTC0sjCyMzR2PCKgALISlz</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data processor with flexible data encryption</title><source>esp@cenet</source><creator>BROWN; DAVID L ; POLANSKY; PAUL J ; POMBO; RAUL A</creator><creatorcontrib>BROWN; DAVID L ; POLANSKY; PAUL J ; POMBO; RAUL A</creatorcontrib><description>A data processor (20) which flexibly encrypts data within different address ranges includes an encryption determination circuit (50) to monitor an address conducted on an internal address bus (22) and when the address is within certain predefined ranges, perform encryption or decryption of address and/or data. For example the encryption determination circuit (50) may be used to selectively enable a data encryption-decryption circuit (60). When the data encryption-decryption circuit (60) is disabled, data conducted on an internal data bus (23) becomes "cleartext", i.e., non-encrypted. In one embodiment, the data encryption-decryption is performed in partial dependence on the address itself, and the address conducted to the external address bus is itself selectively encrypted as well.</description><edition>6</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19990406&amp;DB=EPODOC&amp;CC=US&amp;NR=5892826A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19990406&amp;DB=EPODOC&amp;CC=US&amp;NR=5892826A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BROWN; DAVID L</creatorcontrib><creatorcontrib>POLANSKY; PAUL J</creatorcontrib><creatorcontrib>POMBO; RAUL A</creatorcontrib><title>Data processor with flexible data encryption</title><description>A data processor (20) which flexibly encrypts data within different address ranges includes an encryption determination circuit (50) to monitor an address conducted on an internal address bus (22) and when the address is within certain predefined ranges, perform encryption or decryption of address and/or data. For example the encryption determination circuit (50) may be used to selectively enable a data encryption-decryption circuit (60). When the data encryption-decryption circuit (60) is disabled, data conducted on an internal data bus (23) becomes "cleartext", i.e., non-encrypted. In one embodiment, the data encryption-decryption is performed in partial dependence on the address itself, and the address conducted to the external address bus is itself selectively encrypted as well.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBxSSxJVCgoyk9OLS7OL1IozyzJUEjLSa3ITMpJVUgBSabmJRdVFpRk5ufxMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JL40GBTC0sjCyMzR2PCKgALISlz</recordid><startdate>19990406</startdate><enddate>19990406</enddate><creator>BROWN; DAVID L</creator><creator>POLANSKY; PAUL J</creator><creator>POMBO; RAUL A</creator><scope>EVB</scope></search><sort><creationdate>19990406</creationdate><title>Data processor with flexible data encryption</title><author>BROWN; DAVID L ; POLANSKY; PAUL J ; POMBO; RAUL A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5892826A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>BROWN; DAVID L</creatorcontrib><creatorcontrib>POLANSKY; PAUL J</creatorcontrib><creatorcontrib>POMBO; RAUL A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BROWN; DAVID L</au><au>POLANSKY; PAUL J</au><au>POMBO; RAUL A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data processor with flexible data encryption</title><date>1999-04-06</date><risdate>1999</risdate><abstract>A data processor (20) which flexibly encrypts data within different address ranges includes an encryption determination circuit (50) to monitor an address conducted on an internal address bus (22) and when the address is within certain predefined ranges, perform encryption or decryption of address and/or data. For example the encryption determination circuit (50) may be used to selectively enable a data encryption-decryption circuit (60). When the data encryption-decryption circuit (60) is disabled, data conducted on an internal data bus (23) becomes "cleartext", i.e., non-encrypted. In one embodiment, the data encryption-decryption is performed in partial dependence on the address itself, and the address conducted to the external address bus is itself selectively encrypted as well.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US5892826A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Data processor with flexible data encryption
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T01%3A13%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BROWN;%20DAVID%20L&rft.date=1999-04-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS5892826A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true