Isolated scan paths

Isolated scan paths

A method of isolating scan paths in an integrated circuit to reduce the RC delay associated with the scan paths and reduce power consumption, and to further enhance the capacitive decoupling of the power supply to reduce noise. The scan path can be connected to a data-storage element (latch or flip-...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: WALTHER, RONALD GENE
Format: Patent
Sprache:eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator WALTHER
RONALD GENE
description A method of isolating scan paths in an integrated circuit to reduce the RC delay associated with the scan paths and reduce power consumption, and to further enhance the capacitive decoupling of the power supply to reduce noise. The scan path can be connected to a data-storage element (latch or flip-flop) by a CMOS transmission gate, a single PMOS or NMOS transistor, or a logic gate (such as a NAND gate). The data-storage element is tested using either a scan-enable line, or the scan clock which is also connected to the data-storage element as an input. When the scan-enable line (or scan clock) is turned on, the scan path is connected to the output of the data-storage element.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5887004A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5887004A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5887004A3</originalsourceid><addsrcrecordid>eNrjZBD2LM7PSSxJTVEoTk7MUyhILMko5mFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8aHBphYW5gYGJo7GhFUAAJ_yH54</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Isolated scan paths</title><source>esp@cenet</source><creator>WALTHER; RONALD GENE</creator><creatorcontrib>WALTHER; RONALD GENE</creatorcontrib><description>A method of isolating scan paths in an integrated circuit to reduce the RC delay associated with the scan paths and reduce power consumption, and to further enhance the capacitive decoupling of the power supply to reduce noise. The scan path can be connected to a data-storage element (latch or flip-flop) by a CMOS transmission gate, a single PMOS or NMOS transistor, or a logic gate (such as a NAND gate). The data-storage element is tested using either a scan-enable line, or the scan clock which is also connected to the data-storage element as an input. When the scan-enable line (or scan clock) is turned on, the scan path is connected to the output of the data-storage element.</description><edition>6</edition><language>eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19990323&amp;DB=EPODOC&amp;CC=US&amp;NR=5887004A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19990323&amp;DB=EPODOC&amp;CC=US&amp;NR=5887004A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WALTHER; RONALD GENE</creatorcontrib><title>Isolated scan paths</title><description>A method of isolating scan paths in an integrated circuit to reduce the RC delay associated with the scan paths and reduce power consumption, and to further enhance the capacitive decoupling of the power supply to reduce noise. The scan path can be connected to a data-storage element (latch or flip-flop) by a CMOS transmission gate, a single PMOS or NMOS transistor, or a logic gate (such as a NAND gate). The data-storage element is tested using either a scan-enable line, or the scan clock which is also connected to the data-storage element as an input. When the scan-enable line (or scan clock) is turned on, the scan path is connected to the output of the data-storage element.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBD2LM7PSSxJTVEoTk7MUyhILMko5mFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8aHBphYW5gYGJo7GhFUAAJ_yH54</recordid><startdate>19990323</startdate><enddate>19990323</enddate><creator>WALTHER; RONALD GENE</creator><scope>EVB</scope></search><sort><creationdate>19990323</creationdate><title>Isolated scan paths</title><author>WALTHER; RONALD GENE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5887004A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>WALTHER; RONALD GENE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WALTHER; RONALD GENE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Isolated scan paths</title><date>1999-03-23</date><risdate>1999</risdate><abstract>A method of isolating scan paths in an integrated circuit to reduce the RC delay associated with the scan paths and reduce power consumption, and to further enhance the capacitive decoupling of the power supply to reduce noise. The scan path can be connected to a data-storage element (latch or flip-flop) by a CMOS transmission gate, a single PMOS or NMOS transistor, or a logic gate (such as a NAND gate). The data-storage element is tested using either a scan-enable line, or the scan clock which is also connected to the data-storage element as an input. When the scan-enable line (or scan clock) is turned on, the scan path is connected to the output of the data-storage element.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US5887004A
source esp@cenet
subjects MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
title Isolated scan paths
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T04%3A58%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WALTHER;%20RONALD%20GENE&rft.date=1999-03-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS5887004A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true