Input comparison circuitry and method for a programmable state machine

Method for decoding inputs in a programmable state machine, including the following steps: bit-wise comparing state machine inputs with select information to produce bit-wise comparison results; determining the logical AND of the bit-wise comparison results; and determining the logical EXCLUSIVE OR of a negate indicator and the logical AND. In a further embodiment, a step of bit-wise ORing the comparison results with mask information is performed before the logical AND step. Circuitry for implementing the method: A bit-wise comparator has two sets of inputs. Its first set of inputs is coupled to state machine input signals. Its second set of inputs is coupled to select information. It is operable to produce bit-wise comparator outputs that indicate the results of bit-wise comparing the state machine input signals with the select information. AND circuitry has an AND circuitry output to indicate the logical AND of the comparator outputs. An EXCLUSIVE OR gate has its first input coupled to the AND circuitry output and has its second input coupled to a negate indicator. The output of the EXCLUSIVE OR gate constitutes the output of the inventive input comparison circuitry. In further embodiments, bit-wise OR circuitry may be interposed between the comparator and the AND circuitry. Such bit-wise OR circuitry may be used for masking by coupling its first set of inputs to the comparator outputs and coupling its second set of inputs to mask information. In the latter embodiment, the bit-wise results of the OR circuitry are ANDed by the AND circuitry.