Testable programmable gate array and associated LSSD/deterministic test methodology
A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subs...
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creator | BOTALA SALLY LARSEN WENDELL RAY BEEBE WAYNE KEVIN GOULD SCOTT WHITNEY KEYSER III FRANK RAY PALMER RONALD RAYMOND WORTH BRIAN |
description | A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5867507A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5867507A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5867507A3</originalsourceid><addsrcrecordid>eNqFjLsKAjEQRdNYiPoNzg-IgqxrKz6wsMtaL2MyGwN5kZlm_95F7K0u53C4c6U7YsFXICg1u4oxfsGhEGCtOAImC8icjZ-chYfWl60loRp98izegEwXEEne2eaQ3bhUswED0-q3C7W-XbvzfUMl98QFDSWS_qmb46Ftdu1p_7_4AKMtODQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Testable programmable gate array and associated LSSD/deterministic test methodology</title><source>esp@cenet</source><creator>BOTALA; SALLY ; LARSEN; WENDELL RAY ; BEEBE; WAYNE KEVIN ; GOULD; SCOTT WHITNEY ; KEYSER III; FRANK RAY ; PALMER; RONALD RAYMOND ; WORTH; BRIAN</creator><creatorcontrib>BOTALA; SALLY ; LARSEN; WENDELL RAY ; BEEBE; WAYNE KEVIN ; GOULD; SCOTT WHITNEY ; KEYSER III; FRANK RAY ; PALMER; RONALD RAYMOND ; WORTH; BRIAN</creatorcontrib><description>A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990202&DB=EPODOC&CC=US&NR=5867507A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990202&DB=EPODOC&CC=US&NR=5867507A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BOTALA; SALLY</creatorcontrib><creatorcontrib>LARSEN; WENDELL RAY</creatorcontrib><creatorcontrib>BEEBE; WAYNE KEVIN</creatorcontrib><creatorcontrib>GOULD; SCOTT WHITNEY</creatorcontrib><creatorcontrib>KEYSER III; FRANK RAY</creatorcontrib><creatorcontrib>PALMER; RONALD RAYMOND</creatorcontrib><creatorcontrib>WORTH; BRIAN</creatorcontrib><title>Testable programmable gate array and associated LSSD/deterministic test methodology</title><description>A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFjLsKAjEQRdNYiPoNzg-IgqxrKz6wsMtaL2MyGwN5kZlm_95F7K0u53C4c6U7YsFXICg1u4oxfsGhEGCtOAImC8icjZ-chYfWl60loRp98izegEwXEEne2eaQ3bhUswED0-q3C7W-XbvzfUMl98QFDSWS_qmb46Ftdu1p_7_4AKMtODQ</recordid><startdate>19990202</startdate><enddate>19990202</enddate><creator>BOTALA; SALLY</creator><creator>LARSEN; WENDELL RAY</creator><creator>BEEBE; WAYNE KEVIN</creator><creator>GOULD; SCOTT WHITNEY</creator><creator>KEYSER III; FRANK RAY</creator><creator>PALMER; RONALD RAYMOND</creator><creator>WORTH; BRIAN</creator><scope>EVB</scope></search><sort><creationdate>19990202</creationdate><title>Testable programmable gate array and associated LSSD/deterministic test methodology</title><author>BOTALA; SALLY ; LARSEN; WENDELL RAY ; BEEBE; WAYNE KEVIN ; GOULD; SCOTT WHITNEY ; KEYSER III; FRANK RAY ; PALMER; RONALD RAYMOND ; WORTH; BRIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5867507A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>BOTALA; SALLY</creatorcontrib><creatorcontrib>LARSEN; WENDELL RAY</creatorcontrib><creatorcontrib>BEEBE; WAYNE KEVIN</creatorcontrib><creatorcontrib>GOULD; SCOTT WHITNEY</creatorcontrib><creatorcontrib>KEYSER III; FRANK RAY</creatorcontrib><creatorcontrib>PALMER; RONALD RAYMOND</creatorcontrib><creatorcontrib>WORTH; BRIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BOTALA; SALLY</au><au>LARSEN; WENDELL RAY</au><au>BEEBE; WAYNE KEVIN</au><au>GOULD; SCOTT WHITNEY</au><au>KEYSER III; FRANK RAY</au><au>PALMER; RONALD RAYMOND</au><au>WORTH; BRIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Testable programmable gate array and associated LSSD/deterministic test methodology</title><date>1999-02-02</date><risdate>1999</risdate><abstract>A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
title | Testable programmable gate array and associated LSSD/deterministic test methodology |
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