Method and apparatus for powering down an integrated circuit transparently and its phase locked loop
A method and apparatus for powering down a microprocessor in a computer system. The method and apparatus includes a phase locked loop (PLL) circuit, wherein the phase locked loop generates bus clock signals for clocking the operations on the bus and core clock signals for clocking the core of the pr...
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| creator | BEUTLER ROBERT R CONARY JAMES W |
| description | A method and apparatus for powering down a microprocessor in a computer system. The method and apparatus includes a phase locked loop (PLL) circuit, wherein the phase locked loop generates bus clock signals for clocking the operations on the bus and core clock signals for clocking the core of the processor in response to global clock signal of the computer system. The microprocessor includes circuitry for processing data synchronous with the core clock signals. The method and circuit also includes circuitry for placing the processor in a reduced power consumption state in response to the execution of a power down instruction. In this manner, the computer system reduces power consumption. |
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The method and apparatus includes a phase locked loop (PLL) circuit, wherein the phase locked loop generates bus clock signals for clocking the operations on the bus and core clock signals for clocking the core of the processor in response to global clock signal of the computer system. The microprocessor includes circuitry for processing data synchronous with the core clock signals. The method and circuit also includes circuitry for placing the processor in a reduced power consumption state in response to the execution of a power down instruction. In this manner, the computer system reduces power consumption.</description><edition>6</edition><language>eng</language><subject>CALCULATING ; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. 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The method and apparatus includes a phase locked loop (PLL) circuit, wherein the phase locked loop generates bus clock signals for clocking the operations on the bus and core clock signals for clocking the core of the processor in response to global clock signal of the computer system. The microprocessor includes circuitry for processing data synchronous with the core clock signals. The method and circuit also includes circuitry for placing the processor in a reduced power consumption state in response to the execution of a power down instruction. In this manner, the computer system reduces power consumption.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS PHYSICS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE |
| title | Method and apparatus for powering down an integrated circuit transparently and its phase locked loop |
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