Central processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addresses

A central processing unit (CPU) of a computer and a method for reducing memory latencies in a computer memory hierarchy are described. The CPU includes an external cache controller and a primary memory controller. An instruction buffer in the primary memory controller stores an address from a primar...

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Bibliographische Detailangaben

Hauptverfasser:	CHERABUDDI, RAJASEKHAR
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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