Processor architecture providing speculative, out of order execution of instructions and trap handling

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SCHULTZ, MERLE A, LIGHTNER, BRUCE D, SPRACKLEN, JOHN E, POPESCU, VALERI, GIBSON, GARY A
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!