Power-up detector circuit
An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied....
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creator | FREYMAN RONALD LAMAR HUNTER MICHAEL JAMES |
description | An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions. In a preferred embodiment, the second capacitor is effectively disabled at low power supply voltages. This facilitates conduction of the discharge transistor for power supply voltage interruptions resulting from slow changes (low slew rate) in the power supply voltage. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5828251A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5828251A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5828251A3</originalsourceid><addsrcrecordid>eNrjZJAMyC9PLdItLVBISS1JTS7JL1JIzixKLs0s4WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8aHBphZGFkamho7GhFUAAKPTIhQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Power-up detector circuit</title><source>esp@cenet</source><creator>FREYMAN; RONALD LAMAR ; HUNTER; MICHAEL JAMES</creator><creatorcontrib>FREYMAN; RONALD LAMAR ; HUNTER; MICHAEL JAMES</creatorcontrib><description>An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions. In a preferred embodiment, the second capacitor is effectively disabled at low power supply voltages. This facilitates conduction of the discharge transistor for power supply voltage interruptions resulting from slow changes (low slew rate) in the power supply voltage.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>1998</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19981027&DB=EPODOC&CC=US&NR=5828251A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19981027&DB=EPODOC&CC=US&NR=5828251A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FREYMAN; RONALD LAMAR</creatorcontrib><creatorcontrib>HUNTER; MICHAEL JAMES</creatorcontrib><title>Power-up detector circuit</title><description>An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions. In a preferred embodiment, the second capacitor is effectively disabled at low power supply voltages. This facilitates conduction of the discharge transistor for power supply voltage interruptions resulting from slow changes (low slew rate) in the power supply voltage.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1998</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAMyC9PLdItLVBISS1JTS7JL1JIzixKLs0s4WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8aHBphZGFkamho7GhFUAAKPTIhQ</recordid><startdate>19981027</startdate><enddate>19981027</enddate><creator>FREYMAN; RONALD LAMAR</creator><creator>HUNTER; MICHAEL JAMES</creator><scope>EVB</scope></search><sort><creationdate>19981027</creationdate><title>Power-up detector circuit</title><author>FREYMAN; RONALD LAMAR ; HUNTER; MICHAEL JAMES</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5828251A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1998</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>FREYMAN; RONALD LAMAR</creatorcontrib><creatorcontrib>HUNTER; MICHAEL JAMES</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FREYMAN; RONALD LAMAR</au><au>HUNTER; MICHAEL JAMES</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Power-up detector circuit</title><date>1998-10-27</date><risdate>1998</risdate><abstract>An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions. In a preferred embodiment, the second capacitor is effectively disabled at low power supply voltages. This facilitates conduction of the discharge transistor for power supply voltage interruptions resulting from slow changes (low slew rate) in the power supply voltage.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | Power-up detector circuit |
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