Multi-processor system using processors of different speeds

Multi-processor system using processors of different speeds

A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed com...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: PHAM, KHUONG HUU, ARROYO, RONALD XAVIER
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator PHAM
KHUONG HUU
ARROYO
RONALD XAVIER
description A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5802355A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5802355A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5802355A3</originalsourceid><addsrcrecordid>eNrjZLD2Lc0pydQtKMpPTi0uzi9SKK4sLknNVSgtzsxLV4ALFyvkpymkZKalpRal5pUoFBekpqYU8zCwpiXmFKfyQmluBnk31xBnD93Ugvz41OKCxOTUvNSS-NBgUwsDI2NTU0djwioAV58vig</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Multi-processor system using processors of different speeds</title><source>esp@cenet</source><creator>PHAM; KHUONG HUU ; ARROYO; RONALD XAVIER</creator><creatorcontrib>PHAM; KHUONG HUU ; ARROYO; RONALD XAVIER</creatorcontrib><description>A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.</description><edition>6</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1998</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19980901&amp;DB=EPODOC&amp;CC=US&amp;NR=5802355A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19980901&amp;DB=EPODOC&amp;CC=US&amp;NR=5802355A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PHAM; KHUONG HUU</creatorcontrib><creatorcontrib>ARROYO; RONALD XAVIER</creatorcontrib><title>Multi-processor system using processors of different speeds</title><description>A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1998</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD2Lc0pydQtKMpPTi0uzi9SKK4sLknNVSgtzsxLV4ALFyvkpymkZKalpRal5pUoFBekpqYU8zCwpiXmFKfyQmluBnk31xBnD93Ugvz41OKCxOTUvNSS-NBgUwsDI2NTU0djwioAV58vig</recordid><startdate>19980901</startdate><enddate>19980901</enddate><creator>PHAM; KHUONG HUU</creator><creator>ARROYO; RONALD XAVIER</creator><scope>EVB</scope></search><sort><creationdate>19980901</creationdate><title>Multi-processor system using processors of different speeds</title><author>PHAM; KHUONG HUU ; ARROYO; RONALD XAVIER</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5802355A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1998</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>PHAM; KHUONG HUU</creatorcontrib><creatorcontrib>ARROYO; RONALD XAVIER</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PHAM; KHUONG HUU</au><au>ARROYO; RONALD XAVIER</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Multi-processor system using processors of different speeds</title><date>1998-09-01</date><risdate>1998</risdate><abstract>A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US5802355A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Multi-processor system using processors of different speeds
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T19%3A24%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PHAM;%20KHUONG%20HUU&rft.date=1998-09-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS5802355A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true