Method and apparatus for fault tolerant BIOS addressing

An apparatus is described to provide a fault tolerant power-on of a computer system, using a BIOS memory containing a primary power-on system level configuration program for a computer system and a separate memory which contains a subset of the primary power-on system level configuration program. Th...

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Bibliographische Detailangaben

Hauptverfasser:	BERMAN, RACHAEL, CIAFFI, MARCO, SHIRRON, STEPHEN F, HAYES, FIDELMA, PETERSON, KEVIN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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