Semiconductor cap

A method for manufacturing a cap for use in a semiconductor package is disclosed. The semiconductor package includes a semiconductor chip and a substrate. The chip is mounted with the substrate at a chip locus. The method preferably comprises the steps of placing a slug in a die, and exercising the die to cold flow the slug to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperating with the base to establish a well bounded by the walls and the base. The walls terminate in a plane, and the well clears the chip when the cap is mounted on the substrate at the chip locus. The invention further includes a cap for use in a semiconductor package. The cap comprises a structure cold flowed from a slug in a die to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperates with the polygonal base to establish a well bounded by the plurality of walls and the polygonal base. The walls terminate generally in a termination plane, and the well clears the chip when the cap is abuttingly mounted at the termination plane on the substrate at the chip locus.