Arrangement and method for improving room-temperature testability of CMOS integrated circuits optimized for cryogenic temperature operation

Room temperature-testing of an MOS field effect transistor architecture, whose parameters have been optimized for operation at cryogenic temperatures, is facilitated by applying a prescribed reverse body-to-source voltage bias, that modifies the variation of the drain-to-source current vs. gate-to-s...

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Bibliographische Detailangaben

Hauptverfasser:	YOUNG, WILLIAM R, GASNER, JOHN T, HEMMENWAY, DONALD F
Format:	Patent
Sprache:	eng
Schlagworte:	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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