Direct memory access controller having programmable timing

An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.