Method and apparatus for testing the address system of a memory system

A method and apparatus for testing or verifying proper operation of an address system of a memory system are provided. The address system includes a write unit for driving write word lines, based on a write address, and a read unit for driving read word lines, based on a read address. A common addre...

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Hauptverfasser:	SAITOH, TOSHIHARU
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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creator	SAITOH TOSHIHARU
description	A method and apparatus for testing or verifying proper operation of an address system of a memory system are provided. The address system includes a write unit for driving write word lines, based on a write address, and a read unit for driving read word lines, based on a read address. A common address is applied to the write unit and read unit, and the outputs thereof are compared for equivalency, using a verification circuit. Proper operation of the address system is indicated by the verification circuit if the outputs of the write and read units are equivalent, and improper operation is indicated if the outputs are not equivalent.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
title	Method and apparatus for testing the address system of a memory system
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