Interrupt message delivery identified by storage location of received interrupt data
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of...
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creator | GARCIA DAVID J BAKER WILLIAM EDWARD BUNTON WILLIAM PATTERSON HINTIKKA PAUL N CODDINGTON JOHN DEANE MEREDITH SUSAN STONE MILLER STEPHEN H WILLIAMS FRANK A ISWANDHI GEOFFREY I WATSON WILLIAM JOEL FOWLER DANIEL L SONNIER DAVID PAUL |
description | A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take. |
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A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.</description><edition>6</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1997</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19971007&DB=EPODOC&CC=US&NR=5675807A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19971007&DB=EPODOC&CC=US&NR=5675807A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GARCIA; DAVID J</creatorcontrib><creatorcontrib>BAKER; WILLIAM EDWARD</creatorcontrib><creatorcontrib>BUNTON; WILLIAM PATTERSON</creatorcontrib><creatorcontrib>HINTIKKA; PAUL N</creatorcontrib><creatorcontrib>CODDINGTON; JOHN DEANE</creatorcontrib><creatorcontrib>MEREDITH; SUSAN STONE</creatorcontrib><creatorcontrib>MILLER; STEPHEN H</creatorcontrib><creatorcontrib>WILLIAMS; FRANK A</creatorcontrib><creatorcontrib>ISWANDHI; GEOFFREY I</creatorcontrib><creatorcontrib>WATSON; WILLIAM JOEL</creatorcontrib><creatorcontrib>FOWLER; DANIEL L</creatorcontrib><creatorcontrib>SONNIER; DAVID PAUL</creatorcontrib><title>Interrupt message delivery identified by storage location of received interrupt data</title><description>A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. 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subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Interrupt message delivery identified by storage location of received interrupt data |
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