Multi-chip device partitioning process

An efficient method for partitioning, for example, FPGA devices is described which optimizes the number of devices required to implement a design. The method involves generating a hierarchical graph of a feasible bipartition of the cells of the design. Feasible pairs are merged, followed by flatteni...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KUNG, DAVID SHING-KI, REDDY, LAKSHMI NARASIMHA
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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