Non-etch back SOG process using a metal via stud

A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow metal via stud structures, and filling the spaces between the metal via stud structures with a planarizing layer of a composite di...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	TEONG, JENNIFER SU PING
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	TEONG JENNIFER SU PING
description	A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow metal via stud structures, and filling the spaces between the metal via stud structures with a planarizing layer of a composite dielectric, which includes a spin on glass layer. The composite dielectric was deposited by initially using a non-porous, silicon oxide layer, followed by the planarizing spin on glass layer. Therefore metal via fills will interface the non-porous, silicon oxide layer.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5639692A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5639692A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5639692A3</originalsourceid><addsrcrecordid>eNrjZDDwy8_TTS1JzlBISkzOVgj2d1coKMpPTi0uVigtzsxLV0hUyE0tScxRKMtMVCguKU3hYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXxocGmZsaWZpZGjsaEVQAAQRkpoA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Non-etch back SOG process using a metal via stud</title><source>esp@cenet</source><creator>TEONG; JENNIFER SU PING</creator><creatorcontrib>TEONG; JENNIFER SU PING</creatorcontrib><description>A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow metal via stud structures, and filling the spaces between the metal via stud structures with a planarizing layer of a composite dielectric, which includes a spin on glass layer. The composite dielectric was deposited by initially using a non-porous, silicon oxide layer, followed by the planarizing spin on glass layer. Therefore metal via fills will interface the non-porous, silicon oxide layer.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1997</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970617&DB=EPODOC&CC=US&NR=5639692A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970617&DB=EPODOC&CC=US&NR=5639692A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TEONG; JENNIFER SU PING</creatorcontrib><title>Non-etch back SOG process using a metal via stud</title><description>A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow metal via stud structures, and filling the spaces between the metal via stud structures with a planarizing layer of a composite dielectric, which includes a spin on glass layer. The composite dielectric was deposited by initially using a non-porous, silicon oxide layer, followed by the planarizing spin on glass layer. Therefore metal via fills will interface the non-porous, silicon oxide layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1997</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDwy8_TTS1JzlBISkzOVgj2d1coKMpPTi0uVigtzsxLV0hUyE0tScxRKMtMVCguKU3hYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXxocGmZsaWZpZGjsaEVQAAQRkpoA</recordid><startdate>19970617</startdate><enddate>19970617</enddate><creator>TEONG; JENNIFER SU PING</creator><scope>EVB</scope></search><sort><creationdate>19970617</creationdate><title>Non-etch back SOG process using a metal via stud</title><author>TEONG; JENNIFER SU PING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5639692A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1997</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TEONG; JENNIFER SU PING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TEONG; JENNIFER SU PING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Non-etch back SOG process using a metal via stud</title><date>1997-06-17</date><risdate>1997</risdate><abstract>A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow metal via stud structures, and filling the spaces between the metal via stud structures with a planarizing layer of a composite dielectric, which includes a spin on glass layer. The composite dielectric was deposited by initially using a non-porous, silicon oxide layer, followed by the planarizing spin on glass layer. Therefore metal via fills will interface the non-porous, silicon oxide layer.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US5639692A
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Non-etch back SOG process using a metal via stud
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T16%3A08%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TEONG;%20JENNIFER%20SU%20PING&rft.date=1997-06-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS5639692A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true