Semiconductor memory device with bit line and select line arrangement maintaining parasitic capacitance in equilibrium

A semiconductor memory device in which sensing of the memory information stored in a memory cell can be carried out stably, and reliably by equilibrating a parasitic capacitance existing between a select line and its adjacent bit line pair. Each Y select line YS is arranged at a position where it un...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SUZUKI, YUKIHIDE, YOSHIDA, HIROYUKI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
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