Vector processor adopting a memory skewing scheme for preventing degradation of access performance

A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the addr...

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Bibliographische Detailangaben

Hauptverfasser:	INAGAMI, YASUHIRO, TANAKA, TERUO, TAMAKI, YOSHIKO, SAKAKIBARA, TADAYUKI, KITAI, KATSUYOSHI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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