Synchronous address latching for memory arrays

Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the...

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Hauptverfasser:	RASHID, MAMUN, MILLS, DUANE R, FACKENTHAL, RICHARD, ROZMAN, ROD
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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creator	RASHID MAMUN MILLS DUANE R FACKENTHAL RICHARD ROZMAN ROD
description	Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
title	Synchronous address latching for memory arrays
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