Method of manufacturing printed circuit board by a build-up technique

Method of manufacturing printed circuit board by a build-up technique

A method of manufacturing a printed wiring board by a build-up technique improves the bonding force between a conductor circuit and a resin. After the surface of the first conductor pattern is roughened by oxidation, an insulating layer is formed to expose a viahole portion of the first conductor pa...

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Hauptverfasser: HIROSAWA, KOUICHI
Format: Patent
Sprache:eng
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CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
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creator HIROSAWA
KOUICHI
description A method of manufacturing a printed wiring board by a build-up technique improves the bonding force between a conductor circuit and a resin. After the surface of the first conductor pattern is roughened by oxidation, an insulating layer is formed to expose a viahole portion of the first conductor pattern. Then the resin insulating layer is roughened and the board is reduction processed before a plating operation is carried out.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5578341A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5578341A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5578341A3</originalsourceid><addsrcrecordid>eNrjZHD1TS3JyE9RyE9TyE3MK01LTC4pLcrMS1coAJIlqSkKyZlFyaWZJQpJ-YlFKQpJlQqJCkmlmTkpuqUFCiWpyRl5mYWlqTwMrGmJOcWpvFCam0HezTXE2UM3tSA_PrW4IDE5NS-1JD402NTU3MLYxNDRmLAKACYKMnc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of manufacturing printed circuit board by a build-up technique</title><source>esp@cenet</source><creator>HIROSAWA; KOUICHI</creator><creatorcontrib>HIROSAWA; KOUICHI</creatorcontrib><description>A method of manufacturing a printed wiring board by a build-up technique improves the bonding force between a conductor circuit and a resin. After the surface of the first conductor pattern is roughened by oxidation, an insulating layer is formed to expose a viahole portion of the first conductor pattern. Then the resin insulating layer is roughened and the board is reduction processed before a plating operation is carried out.</description><edition>6</edition><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>1996</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19961126&amp;DB=EPODOC&amp;CC=US&amp;NR=5578341A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19961126&amp;DB=EPODOC&amp;CC=US&amp;NR=5578341A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIROSAWA; KOUICHI</creatorcontrib><title>Method of manufacturing printed circuit board by a build-up technique</title><description>A method of manufacturing a printed wiring board by a build-up technique improves the bonding force between a conductor circuit and a resin. After the surface of the first conductor pattern is roughened by oxidation, an insulating layer is formed to expose a viahole portion of the first conductor pattern. Then the resin insulating layer is roughened and the board is reduction processed before a plating operation is carried out.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1996</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD1TS3JyE9RyE9TyE3MK01LTC4pLcrMS1coAJIlqSkKyZlFyaWZJQpJ-YlFKQpJlQqJCkmlmTkpuqUFCiWpyRl5mYWlqTwMrGmJOcWpvFCam0HezTXE2UM3tSA_PrW4IDE5NS-1JD402NTU3MLYxNDRmLAKACYKMnc</recordid><startdate>19961126</startdate><enddate>19961126</enddate><creator>HIROSAWA; KOUICHI</creator><scope>EVB</scope></search><sort><creationdate>19961126</creationdate><title>Method of manufacturing printed circuit board by a build-up technique</title><author>HIROSAWA; KOUICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5578341A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1996</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>HIROSAWA; KOUICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIROSAWA; KOUICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of manufacturing printed circuit board by a build-up technique</title><date>1996-11-26</date><risdate>1996</risdate><abstract>A method of manufacturing a printed wiring board by a build-up technique improves the bonding force between a conductor circuit and a resin. After the surface of the first conductor pattern is roughened by oxidation, an insulating layer is formed to expose a viahole portion of the first conductor pattern. Then the resin insulating layer is roughened and the board is reduction processed before a plating operation is carried out.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
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subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title Method of manufacturing printed circuit board by a build-up technique
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T02%3A38%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HIROSAWA;%20KOUICHI&rft.date=1996-11-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS5578341A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true