System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal

Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (...

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Bibliographische Detailangaben

Hauptverfasser:	WOLFORD, JEFF W, CULLEY, PAUL R, MORIARTY, MICHAEL, MELO, MARIA L, SCHNELL, ARNOLD T
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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