Single layer leadframe design with groundplane capability
An electronic package including a leadframe that includes a single layer of an electrically conducting material, a semiconductor chip support, a common ground portion surrounding the semiconductor chip support and electrically connected thereto, a plurality of signal leads electrically isolated from...
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| creator | DIFFENDERFER STEVEN J SHAUKATULLAH HUSSAIN |
| description | An electronic package including a leadframe that includes a single layer of an electrically conducting material, a semiconductor chip support, a common ground portion surrounding the semiconductor chip support and electrically connected thereto, a plurality of signal leads electrically isolated from each other and from the common ground portion, and a plurality of ground leads electrically connected to the common ground portion. A semiconductor chip including a plurality of signal sites and a plurality of ground sites is mounted on the semiconductor chip support of the leadframe. A plurality of electrical connections are provided between selected ones of the signal sites to respective ones of the signal leads and between selected ones of the ground sites to respective ones of the ground leads. A protective enclosure is provided substantially about the semiconductor device, the semiconductor chip support, the common ground portion of the leadframe, and at least a portion of the signal leads. |
| format | Patent |
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A semiconductor chip including a plurality of signal sites and a plurality of ground sites is mounted on the semiconductor chip support of the leadframe. A plurality of electrical connections are provided between selected ones of the signal sites to respective ones of the signal leads and between selected ones of the ground sites to respective ones of the ground leads. A protective enclosure is provided substantially about the semiconductor device, the semiconductor chip support, the common ground portion of the leadframe, and at least a portion of the signal leads.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><creationdate>1996</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19960806&DB=EPODOC&CC=US&NR=5543657A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19960806&DB=EPODOC&CC=US&NR=5543657A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DIFFENDERFER; STEVEN J</creatorcontrib><creatorcontrib>SHAUKATULLAH; HUSSAIN</creatorcontrib><title>Single layer leadframe design with groundplane capability</title><description>An electronic package including a leadframe that includes a single layer of an electrically conducting material, a semiconductor chip support, a common ground portion surrounding the semiconductor chip support and electrically connected thereto, a plurality of signal leads electrically isolated from each other and from the common ground portion, and a plurality of ground leads electrically connected to the common ground portion. A semiconductor chip including a plurality of signal sites and a plurality of ground sites is mounted on the semiconductor chip support of the leadframe. A plurality of electrical connections are provided between selected ones of the signal sites to respective ones of the signal leads and between selected ones of the ground sites to respective ones of the ground leads. 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A semiconductor chip including a plurality of signal sites and a plurality of ground sites is mounted on the semiconductor chip support of the leadframe. A plurality of electrical connections are provided between selected ones of the signal sites to respective ones of the signal leads and between selected ones of the ground sites to respective ones of the ground leads. A protective enclosure is provided substantially about the semiconductor device, the semiconductor chip support, the common ground portion of the leadframe, and at least a portion of the signal leads.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS |
| title | Single layer leadframe design with groundplane capability |
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