Logic allocator for a programmable logic device

Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, pro...

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Bibliographische Detailangaben

Hauptverfasser:	ILGENSTEIN, KERRY A, AGRAWAL, OM P, MOENCH, JERRY D
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
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